1. Field of the Invention
The present invention relates to the general field of semiconductor device protection circuits wherein such circuits protect a semiconductor device by minimizing either applied voltage, through current and/or power dissipation so as to enable the device to survive. More particularly, the present invention is directed to protecting semiconductor devices, such as field effect transistors (FETs), so that they can survive excessive voltages, currents and/or power dissipation which may be produced during load dump conditions.
2. Description of the Prior Art
FETs which drive high current loads have been provided with protection circuits which turn the FET off if conditions such as overcurrent, excessive FET power dissipation or excessive FET temperature are detected. U.S. Pat. No. 4,896,245 to Qualich and pending U.S. patent application Ser. No. 07/355,228, filed May 22, 1989 to Edwards et al. are examples of such prior protection circuits. However, such protection circuits typically do not provide sufficient protection for the FET during load dump conditions during which substantial excessive voltages can be applied between the drain and source terminals potentially causing undesired avalanche breakdown of some internal junctions of the FET semiconductor device. This can occur regardless of the operation of the above noted turn-off circuits.
Some prior circuits use a zener diode connected between B+ and ground to limit the load dump overvoltage applied to a high current rated FET. However, this solution requires the use of high current rated components for the limiting circuitry, and therefore is undesirable.
Some FET protection circuits have utilized a zener diode connected between the drain and gate electrodes to protect the FET by turning the device on in response to a load dump voltage in excess of the zener diode breakdown voltage. However, such circuits may not provide sufficient protection since they can result in excessive FET power dissipation during repetitive switching of the FET on and off during the load dump transient. Pending U.S. patent application Ser. No. 07/484,313, filed Feb. 26, 1990 to Edwards proposes one solution to this problem by utilizing a capacitor as a supplementary supply of operative power to maintain the FET on during a load dump condition. However, such circuitry may require the use of a costly energy storage element, such as a large capacitor, which can't be provided on an integrated circuit, and many times this is undesirable. In addition, it maybe difficult to determine the end of the load dump transient condition such that the FET device only remains on during the existence of such a condition. Also, if a zener diode is directly connected between a FET's gate and drain electrodes and is used to turn on and maintain the FET on in response to load dump, the FET can be subject to failure due to excessive power dissipation during load dump. This is because a substantial drain to source voltage (V.sub.DS) will exist during load dump due to the zener diode while a substantial current is passed through the FET device.